Design of Fast, Low Power 16-Bit Multiplier Using Vedic Mathematics by Amit Gupta

Design of Fast, Low Power 16-Bit Multiplier Using Vedic Mathematics

Amit Gupta

156 pages missing pub info (editions)

nonfiction art technology
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Description

Low power, high speed binary multiplier is an essential component of digital computers. Many architectures of multiplier based on Booth multiplication and array multiplication algorithms have been implemented. The array multiplier using Wallace tr...

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